FEC Software Decoders Hall of Fame

This page presents a Channel Coding Software Decoders "Hall of Fame". It allows to see at a glance what has been achieved, what can be expected from today software decoders, and easily compare their respective characteristics. For now, three wide code families are considered: the Turbo codes (LTE, LTE-Advanced, CCSDS, etc.), the Low-Density Parity-Check (LDPC) codes (Wi-Fi, WiMAX, CCSDS, WRAN, DVB-S2, etc.), and the recently introduced Polar codes (candidates for 5G).

All the presented results, collected from the state-of-the-art research papers published in the field, consider a BPSK (Bit Phase-Shift Keying) modulation/demodulation and an AWGN (Additive White Gaussian Noise) channel.

This Hall of Fame strives to present results as fairly as possible: for example, early termination criteria are not taken into consideration while computing throughput, in order to compare raw performances using a consistent method. It remains possible, however, for typos/glitches/mistakes to have inadvertantly made it to the scoreboard. In that eventuality, do not hesitate to contact us. If you would like to have your decoder listed as well in the Hall of Fame: please send us the corresponding research paper references, and we will be delighted to add them.

In blue, the results simulated or reproducible with AFF3CT: our Open-source communication chain dedicated to the Forward Error Correction (FEC) simulations.

Last update: 2018-10-02.

Belief Propagation (BP)

Work Year Platform Implem. Pre. Inter Code i Lat. Thr. NThr. TNDC Ed
[1] 2008 8800 GT F-SPA+ 32 1 (4096, 2048) 6 467000 0.01 0.001 0.000006 105000000
[2] 2008 CELL F-MS 8 96 (1248, 624) 25 3653 32.8 16.4 0.052 6098
[3] 2009 8800 GTX F-SPA 32 - (1908, 1696) 50 - 0.08 0.08 0.0005 2200000
[4] 2011 8800 GTX F-SPA 8 - (8000, 4000) 50 - 10.1 10.1 0.058 17426
[4] 2011 CELL F-SPA 32 24 (1024, 512) 50 1719 14.3 14.3 0.181 13986
[4] 2011 2xE5530 F-SPA 32 1 (8000, 4000) 50 13115 0.61 0.61 0.0079 262295
[5] 2011 CELL F-OMS 8 1 (960, 480) 15 74 13.0 3.9 0.0095 51282
[6] 2011 Tesla C2050 F-MS 8 16 (64800, 21600) 30 13275 78.1 46.86 0.091 5271
[7] 2011 GTX 470 F-LSPA+ 32 300 (1944, 972) 50 57743 10.1 10.1 0.018 21287
[8] 2011 GTX 285 F-SPA+ 32 1 (2304, 1152) 15 1097 2.1 0.63 0.0018 323810
[9] 2011 Tesla C1060 F-LSPA 32 1 (8000, 4000) 50 8638 0.92 0.92 0.0029 217391
[10] 2011 GTX 470 F-LSPA 32 224 (2304, 1152) 10 10533 49.0 9.8 0.018 21939
[11] 2012 GTX 480 F-SPA+ 32 1 (2048, 1723) 50 426 4.8 4.8 0.0071 52083
[12] 2012 HD 5870 F-MS 8 500 (8000, 4000) 10 22222 180.0 36.0 0.075 5222
[12] 2012 Tesla C2050 F-MS 8 500 (8000, 4000) 10 20000 200.0 40.0 0.078 6175
[13] 2012 Tesla C2050 F-MS 8 128 (16200, 8100) 50 26083 79.5 79.5 0.154 3107
[13] 2012 i7-950 F-MS 8 128 (16200, 8100) 50 113934 18.2 18.2 0.093 7143
[14] 2013 i7-3960X F-NMS+ 8 12 (9216, 4608) 10 1202 92.0 18.4 0.058 7065
[15] 2013 GTX 580 CL-MS 8 1024 (2304, 1152) 5 3322 710.2 142.0 0.180 1718
[16] 2013 i7-2600K L-OMS 8 1 (524280, 262140) 5 17420 30.1 3.0 0.055 31667
[17] 2013 Cortex-A9 F-MS 8 128 (16200, 8100) 20 592457 3.5 1.4 0.014 2857
[18] 2013 GTX TITAN F-NMS+ 32 50 (2304, 1152) 10 1266 304.2 60.8 0.027 4112
[18] 2013 GTX TITAN F-NMS+ 32 6 (2304, 1152) 10 207 66.8 13.4 0.006 18657
[19] 2014 GTX 660 Ti F-SPA 8 12544 (8000, 4000) 50 954100 105.2 105.2 0.085 1426
[20] 2014 GTX 660 HL-OMS 8 16384 (1944, 972) 10 34362 926.9 185.4 0.049 755
[22] 2016 i7-4960HQ HL-NMS+ 8 128 (2304, 1152) 50 1359 217 217 0.500 217
[23] 2016 GTX 470 PL-MS 32 256 (1944, 972) 10 9739 51.1 10.2 0.019 21078
[25] 2017 GTX TITAN X F-MS 32 - (1944, 972) 10 2.1 913 182.6 0.036 1369
[26] 2017 GTX TITAN X F-MS+BCH 32 28 (1944, 972) 10 32.8 1660 332.0 0.065 753
[27] 2017 i7-5650U HL-OMS+ 8 1 (2304, 1152) 10 11.9 385 77 0.401 123
[28] 2018 GTX TITAN Xp F-OMS 32 1 (64800, 21600) 50 - 160 160 0.026 1563

Linear Programming (LP)

Work Year Platform Implem. Pre. Inter Code i Lat. Thr. NThr. TNDC Ed
[21] 2016 i7-4960HQ F-ADMM 32 4 (2304, 1152) 8 1511 6.1 0.98 0.009 47959
[24] 2016 i7-4960HQ HL-ADMM 32 32 (2304, 1152) 100 13755 5.4 10.8 0.099 4352

References

  1. S. Wang, S. Cheng, and Q. Wu, “A Parallel Decoding Algorithm of LDPC Codes using CUDA,” in Proceedings of the IEEE Asilomar Conference on Signals, Systems, and Computers (ACSSC), October 2008.
  2. G. Falcao, V. Silva, L. Sousa, and J. Marinho, “High Coded Data Rate and Multicodeword WiMAX LDPC Decoding on the Cell/BE,” IET Electronics Letters, November 2008.
  3. G. Falcao, S. Yamagiwa, V. Silva, and L. Sousa, “Parallel LDPC Decoding on GPUs Using a Stream-Based Computing Approach,” Springer Journal of Computer Science and Technology (JCST), September 2009.
  4. G. Falcao, L. Sousa, and V. Silva, “Massively LDPC Decoding on Multicore Architectures,” IEEE Transactions on Parallel and Distributed Systems (TPDS), February 2011.
  5. J. Zhao, M. Zhao, H. Yang, J. Chen, X. Chen, and J. Wang, “High Performance LDPC Decoder on CELL BE for WiMAX System,” in Proceedings of the IEEE International Conference on Communications and Mobile Computing (CMC), April 2011.
  6. G. Falcao, J. Andrade, V. Silva, and L. Sousa, “GPU-Based DVBS2 LDPC Decoder with High Throughput and Fast Error Floor Detection,” IET Electronics Letters, April 2011.
  7. G. Wang, M. Wu, Y. Sun, and J. R. Cavallaro, “A Massively Parallel Implementation of QC-LDPC Decoder on GPU,” in Proceedings of the IEEE Symposium on Application Specific Processors (SASP), June 2011.
  8. H. Ji, J. Cho, and W. Sung, “Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU,” Springer Journal of Signal Processing Systems (JSPS), July 2011.
  9. C-C. Chang, Y-L. Chang, M-Y. Huang and B. Huang, “Accelerating Regular LDPC Code Decoders on GPUs,” IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing (J-STARS), September 2011.
  10. G. Wang, M. Wu, Y. Sun, and J. R. Cavallaro, “GPU Accelerated Scalable Parallel Decoding of LDPC Codes,” in Proceedings of the IEEE Asilomar Conference on Signals, Systems, and Computers (ACSSC), November 2011.
  11. S. Kang and J. Moon, “Parallel LDPC Decoder Implementation on GPU Based on Unbalanced Memory Coalescing,” in Proceedings of the IEEE International Conference on Communications (ICC), June 2012.
  12. G. Falcao, V. Silva, L. Sousa, and J. Andrade, “Portable LDPC Decoding on Multicores using OpenCL,” IEEE Signal Processing Magazine, July 2012.
  13. S. Gronroos, K. Nybom, and J. Bjorkqvist, “Efficient GPU and CPU-Based LDPC Decoders for Long Codewords,” Springer Journal of Analog Integrated Circuits and Signal Processing (AICSP), November 2012.
  14. X. Pan, X. fan Lu, M. qi Li, and R. fang Song, “A High Throughput LDPC Decoder in CMMB Based on Virtual Radio,” in Proceedings of the IEEE Wireless Communications and Networking Conference Workshops (WCNCW), April 2013.
  15. R. Li, J. Zhou, Y. Dou, S. Guo, D. Zou and S. Wang, “A Multi-Standard Efficient Column-Layered LDPC Decoder for Software Defined Radio on GPUs,” in Proceedings of the IEEE International Workshop on Signal Processing Advances in Wireless Communications (SPAWC), June 2013.
  16. X. Han, K. Niu, and Z. He, “Implementation of IEEE 802.11n LDPC Codes Based on General Purpose Processors,” in Proceedings of the IEEE International Conference on Communication Technology (ICCT), November 2013.
  17. S. Gronroos and J. Bjorkqvist, “Performance Evaluation of LDPC Decoding on a General Purpose Mobile CPU,” in Proceedings of the IEEE Global Conference on Signal and Information Processing (GlobalSIP), December 2013.
  18. G. Wang, M. Wu, B. Yin, and J. R. Cavallaro, “High Throughput Low Latency LDPC Decoding on GPU for SDR Systems,” in Proceedings of the IEEE Global Conference on Signal and Information Processing (GlobalSIP), December 2013.
  19. Y. Lin and W. Niu, “High Throughput LDPC Decoder on GPU,” IEEE Communications Letters (COMML), February 2014.
  20. B. Le Gal, C. Jégo, and J. Crenne, “A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices,” IEEE Embedded Systems Letters (ESL), June 2014.
  21. I. Debbabi, N. Khouja, F. Tlili, B. Le Gal, C. Jégo, “Multicore Implementation of LDPC Decoders Based on ADMM Algorithm,” in Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), March 2016.
  22. B. Le Gal and C. Jégo, “High-Throughput Multi-Core LDPC Decoders Based on x86 Processor,” IEEE Transactions on Parallel and Distributed Systems (TPDS), May 2016.
  23. B. C. Lai, C. Y. Lee, T. H. Chiu, H. K. Kuo and C. K. Chang, “Unified Designs for High Performance LDPC Decoding on GPGPU,” IEEE Transactions on Computers (TC), December 2016.
  24. I. Debbabi, B. Le Gal, N. Khouja, F. Tlili, and C. Jégo, “Real Time LP Decoding of LDPC Codes for High Correction Performance Applications,” IEEE Wireless Communications Letters (WCL), December 2016.
  25. S. Keskin and T. Kocak, “GPU-Based Gigabit LDPC Decoder,” IEEE Communications Letters (COMML), May 2017.
  26. S. Keskin and T. Kocak, “GPU Accelerated Gigabit Level BCH and LDPC Concatenated Coding System,” in Proceedings of the IEEE High Performance Extreme Computing Conference (HPEC), September 2017.
  27. B. Le Gal and C. Jégo, “Low-Latency Software LDPC Decoders for x86 Multi-core Devices,” in Proceedings of the IEEE International Workshop on Signal Processing Systems (SiPS), October 2017.
  28. D. Kun, “High Throughput GPU LDPC Encoder and Decoder for DVB-S2,” in Proceedings of the IEEE Aerospace Conference (AeroConf), March 2018.